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February 1999
PBM 3960/1 Microstepping Controller/ Dual Digital-to-Analog Converter
Description
PBM 3960/1 is a dual 7-bit+sign, Digital-to-Analog Converter (DAC) especially developed to be used together with the PBL 3771/1, Precision Stepper Motor driver in micro-stepping applications. The circuit has a set of input registers connected to an 8-bit data port for easy interfacing directly to a microprocessor. Two registers are used to store the data for each seven-bit DAC, the eighth bit being a sign bit (sign/ magnitude coding). A second set of registers are used for automatic fast/slow current decay control in conjunction with the PBL 3771/1, a feature that greatly improves high-speed micro-stepping performance. The PBM 3960/1 is fabricated in a highspeed CMOS process.
Key Features
* Analog control voltages from 3 V down to 0.0 V. * High-speed microprocessor interface. * Automatic fast/slow current decay control. * Full-scale error 1 LSB. * Interfaces directly with TTL levels and CMOS devices. * Fast conversion speed, 3 s. * Matches PBL 3771.
WR C
DA- Data 1
D E1 CS C D
R
Level 2
R
Level 1
Digit Comp
E1 C
E D
R
CD 1 DA 1
E E2 A0 E3 C D A1 E4 D7 - D0 C D
R R
DA- Data 2
D/A
E D/A Digit Comp E4 C D
R
DA E
2
CD 2
E
Sign 2
POR RESET
R
V ss
Figure 1. Block Diagram.
P B
22-pin plastic DIP 28-pin plastic PLCC
M
M B /1 P 60 39
E
Sign 1
39
PBM 3960/1
60
/1
V DD
V Ref
PBM 3960/1
Maximum Ratings
Parameter Pin no. * Symbol Min Max Unit
Voltage Supply Logic inputs Reference input Current Logic inputs Temperature Storage temperature Operating ambient temperature * refers to DIP package
5 6- 17 1 6- 17
VDD VI VR II TS TJ
-0.3 -0.3 -0.4 -55 -20
6 VDD+ 0.3 VDD+ 0.3 +0.4 +150 +85
V V V mA C C
Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Supply voltage Reference voltage
VDD VR
4.75 0
5.0 2.5
5.25 3.0
V V
t cs CS t as A0-A1 t ds D0-D7 t WR WR
t ch
t ah
t dh
t DAC
DA t pwr Sign, CD
Figure 2. Timing.
t res Reset
t pres Sign, CD
Figure 3. Timing of Reset.
2
PBM 3960/1
Electrical Characteristics
Electrical characteristics over recommended operating conditions.
Parameter Ref. Symbol fig Conditions Min Typ Max Unit
Logic Inputs Reset logic HIGH input voltage Reset logic LOW input voltage Logic HIGH input voltage Logic LOW input voltage Reset input current Input current, other inputs Input capacitance
VIHR VILR VIH VIL IIR II
3.5 0.1 2.0 VSS < VIR < VDD VSS < VI < VDD -0.01 -1 3 2 2 2 2 2 2 2 3 Valid for A0, A1 Valid for D0 - D7 60 60 70 0 0 0 50 80 6 VO = 2.4 V VO = 0.4 V From positive edge of WR. outputs valid, Cload = 120 pF From positive edge of Reset to outputs valid, Cload = 120 pF Reset open, VRef = 2.5 V 9 -13 5 30 60 -5 100 150 0.8 1 1
V V V V mA A pF ns ns ns ns ns ns ns ns k mA mA ns ns
Internal Timing Characteristics Address setup time tas Data setup time tds Chip select setup time tcs Address hold time tah Data hold time tdh Chip select hold time tch Write cycle length tWR Reset cycle lenght tR Reference Input Input resistance Logic Outputs Logic HIGH output current Logic LOW output current Write propagation delay Reset propagation delay DAC Outputs Nominal output voltage Resolution Offset error Gain error Endpoint nonlinearity Differential nonlinearity Load error Power supply sensitivity Conversion speed tDAC RRef IOH IOL tpWR tpR
1.7
2 3
VDA 7 7 7 5, 6
0 7 0.2 0.1 0.2 0.2 0.1 0.1 3
2
(VDA, unloaded - VDA, loaded) Rload = 2.5 k, Code 127 to DAC Code 127 to DAC 4.75 V < VDD < 5.25 V For a full-scale transition to 0.5 LSB of final value, Rload = 2.5 kohm, Cload = 50 pF.
VRef- 1LSB V Bits 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.3 8 LSB s
3
PBM 3960/1
Sign 2
V ref DA 1 Sign 1 CD 1 VDD WR D7 D6 D5 D4 D3
1 2 3 4 5 6 7 8 9 10 11
22 21 20 19
Reset DA 2 Sign 2 CD 2 VSS CS A1 A0 D0 D1 D2
N/C DA 2 Reset
5 6 7 8 9 10 11
CD 2
VSS
CS
28
27
26
4
3
2
1
N/C
A1
A0
25 24
D0 D1 D2 N/C D3 D4 D5
PBM 3960/1N
18 17 16 15 14 13 12
N/C V ref DA 1 N/C
PBM 3960/1QN
23 22 21 20 19
12
13
14
15
16
17
Sign 1
CD 1
VDD
Figure 4. Pin configuration.
Pin Descriptions
Refer to figure 4.
DIP PLCC Symbol Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
9 10 12 13 14 15 16 17 19 20 21 23 24 25 27 28 1 2 3 4 6 7 5 8 11 18 22 26
VRef DA1 Sign1 CD1 VDD WR D7 D6 D5 D4 D3 D2 D1 D0 A0 A1 CS VSS CD2 Sign2 DA2 Reset
Voltage reference supply pin, 2.5 V nominal (3.0 V maximum) Digital-to-Analog 1, voltage output. Output between 0.0 V and VR - 1 LSB. Sign 1, TTL/CMOS level. To be connected directly to PBL 3771 Phase input. Databit D7 is transfered non inverted from PBM 3960/1/1 data input. Current Decay 1, TTL/CMOS level. The signal is automatically generated when decay level is programmed. LOW level = fast current decay. Voltage Drain-Drain, logic supply voltage. Normally +5 V. Write, TTL/CMOS level, input for writing to internal registers. Data is clocked into flip flops on positive edge. Data 7, TTL/CMOS level, input to set data bit 7 in data word. Data 6, TTL/CMOS level, input to set data bit 6 in data word. Data 5, TTL/CMOS level, input to set data bit 5 in data word. Data 4, TTL/CMOS level, input to set data bit 4 in data word. Data 3, TTL/CMOS level, input to set data bit 3 in data word. Data 2, TTL/CMOS level, input to set data bit 2 in data word. Data 1, TTL/CMOS level, input to set data bit 1 in data word. Data 0, TTL/CMOS level, input to set data bit 0 in data word. Address 0, TTL/CMOS level, input to select data transfer, A0 selects between cannel 1 (A0 = LOW) and channel 2 (A0 = HIGH). Address 1, TTL/CMOS level, input to select data transfer. A1 selects between normal D/A register programming (A1 = LOW) and decay level register programming (A1 = HIGH). Chip Select, TTL/CMOS level, input to select chip and activate data transfer from data inputs. LOW level = chip is selected. Voltage Source-Source. Ground pin, 0 V reference for all signals and measurements unless otherwise noted. Current Decay 2, TTL/CMOS level. The signal is automatically generated when decay level is programmed. LOW level = fast current decay . Sign 2. TTL/CMOS level. To be connected directly to PBL 3771 sign input. Data bit D7 is transfered non-inverted from PBM 3960/1 data input. Digital-to-Analog 2, voltage output. Output between 0.0 V and Vref - 1 LSB. Reset, digital input resetting internal registers. HIGH level = Reset, VRes 3.5 V = HIGH level. Pulled low internally. Not Connected Not Connected Not Connected Not Connected Not Connected Not Connected
4
WR
N/C
D7
D6
18
PBM 3960/1
Definition of Terms
Resolution Resolution is defined as the reciprocal of the number of discrete steps in the DAC output. It is directly related to the number of switches or bits within the DAC. For example, PBM 3960/1 has 27, or 128, output levels and therefor has 7 bits resolution. Remember that this is not equal to the number of microsteps available. Linearity Error Linearity error is the maximum deviation from a straight line passing through the end points of the DAC transfer characteristic. It is measured after adjusting for zero and full scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted. Power Supply Sensitivity Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output. Settling Time Full-scale current settling time requires zero-to-full-scale or full-scale-to-zero output change. Settling time is the time required from a code transition until the DAC output reaches within 1/2LSB of the final output value. Full-scale Error Full-scale error is a measure of the output error between an ideal DAC and the actual device output. Differential Non-linearity The difference between any two consecutive codes in the transfer curve from the theoretical 1LSB, is differential non-linearity Monotonic If the output of a DAC increases for increasing digital input code, then the DAC is monotonic. A 7-bit DAC which is monotonic to 7 bits simply means that increasing digital input codes will produce an increasing analog output. PBM 3960/1 is monotonic to 7 bits. different levels for initiation of fast current decay can be selected. The sign outputs generate the phase shifts, i.e., they reverse the current direction in the phase windings. Data Bus Interface PBM 3960/1 is designed to be compatible with 8-bit microprocessors such as the 6800, 6801, 6803, 6808, 6809, 8051, 8085, Z80 and other popular types and their 16/32 bit counter parts in 8 bit data mode. The data bus interface consists of 8 data bits, write signal, chip select, and two address pins. All inputs are TTLcompatible (except reset). The two address pins control data transfer to the four internal D-type registers. Data is transferred according to figure 10 and on the positive edge of the write signal. Current Direction, Sign1 & Sign2 These bits are transferred from D7 when writing in the respective DA register. A0 and A1 must be set according to the data transfer table in figure 10. Current Decay, CD1 & CD2 CD1 and CD2 are two active low signals (LOW = fast current decay). CD1 is active if the previous value of DA-Data1 is strictly larger than the new value of DA-Data1 and the value of the level register LEVEL1 (L61 ... L41) is strictly larger than the new value of DA-Data1. CD1 is updated every time a new value is loaded into DA-Data1. The logic definition of CD1 is: CD1 = NOT{[(D6 ... D0) < (Q61 ... Q01)] AND[(D6 ...D4) < (L61 ... L41)]}
Functional Description
Each DAC channel contains two registers, a digital comparator, a flip flop, and a D/A converter. A block diagram is shown on the first page. One of the registers stores the current level, below which, fast current decay is initiated. The status of the CD outputs determines a fast or slow current decay to be used in the driver. The digital comparator compares each new value with the previous one and the value for the preset level for fast current decay. If the new value is strictly lower than both of the others, a fast current decay condition exists. The flip flop sets the CD output. The CD output is updated each time a new value is loaded into the D/A register. The fast current decay signals are used by the driver circuit, PBL 3771/1, to change the current control scheme of the output stages. This is to avoid motor current dragging which occurs at high stepping rates and during the negative current slopes, as illustrated in figure 9. Eight
Output
Output
Output Actual Gain error Correct Endpoint non-linearity
More than 2 bits
Less than 2 bits
Negative difference
Positive difference
Offset error Full scale Input
Input
Input
Figure 5. Errors in D/A conversion. Differential non-linearity of more than 1 bit, output is non-monotonic.
Figure 6. Errors in D/A conversion. Differential non-linearity of less than 1 bit, output is monotonic.
Figure 7. Errors in D/A conversion. Nonlinearity, gain and offset errors.
5
PBM 3960/1
Where (D6 ... D0) is the new value being sent to DA-Data1 and (Q61 ... Q01) is DAData1's old value. (L61 ... L41) are the three bits for setting the current decay level at LEVEL1. The logic definition of CD2 is analog to CD1: CD2 = NOT{[(D6 ... D0) < (Q62 ... Q02)] AND[(D6 ...D4) < (L62 ... L42)]} Where (L62 ... L42) is the level programmed in channel 2's level register. (D6 ... D0) and (Q62 ... Q02) are the new and old values of DA-Data2. The two level registers, LEVEL1 and LEVEL2, consist of three flip flops each and they are compared against the three most significant bits of the DAData value, sign bit excluded. DA1 and DA2
I2 [mA]
Reset If Reset is not used, leave it disconnected. Reset can be used to measure leakage currents from VDD.
Applications Information
How Many Microsteps? The number of true microsteps that can be obtained depends upon many different variables, such as the number of data bits in the Digital-to-Analog converter, errors in the converter, acceptable torque ripple, single- or double-pulse programming, the motor's electrical, mechanical and magnetic characteristics, etc. Many limits can be found in the motor's ability to perform properly; overcome friction, repeatability, torque linearity, etc. It is important to realize that the number of current levels, 128 (27), is not the number of steps available. 128 is the number of current levels (reference voltage levels) available from each driver stage. Combining a current level in one winding with any of 128 other current levels in the other winding will make up 128 current levels. So expanding this, it is possible to get 16,384 (128 * 128) combinations of different current levels in the two windings. Remember that these 16,384 micro-positions are not all useful, the torque will vary from 100% to 0% and some of the options will make up the same position. For instance, if the current level in one winding is OFF (0%) you can still vary the current in the other winding in 128 levels. All of these combinations will give you the same position but a varying torque. Typical Application
These are the two outputs of DAC1 and DAC2. Input to the DACs are internal data bus (Q61 ... Q01) and (Q62 ... Q02). Reference Voltage VRef
I
VRef is the analog input for the two DACs. Special care in layout, gives a very low voltage drop from pin to resistor. Any VRef between 0.0 V and VDD can be applied, but output might be nonlinear above 3.0 V. Power-on Reset
I1 [mA]
Figure 8a. Assuming that torque is proportional to the current in resp. winding it is possible to draw figure 8b.
This function automatically resets all internal flip flops at power-on. This results in VSS voltage at both DAC outputs and all digital outputs.
T2
T max
[mNm]
DA output [V]
Current dragging
Tnom
Tmin
CD
t
T1
[mNm]
Time
Figure 8b. An example of accessible positions with a given torque deviation/ fullstep. Note that 1:st step sets highest resolution. Data points are exaggerated for illustration purpose. TNom = code 127.
CS 0 0 0 0 1 A0 0 0 1 1 X A1 0 1 0 1 X
Figure 9. Motor current dragging at high step rates and current decay influence. Fast current decay will make it possible for the current to follow the ideal sine curve. Output shown without sign shift.
Data Transfer D7 --> Sign1, (D6--D0) --> (Q61--Q01), New value --> CD1 (D6--D4) --> (L61--L41) D7 --> Sign2, (D6--D0) --> (Q62--Q02), New value --> CD2 (D6--D4) --> (L62--L42) No Transfer
Figure 10. Table showing how data is transfered inside PBM 3960/1.
6
The microstepper solution can be used in a system with or without a microprocessor. Without a microprocessor, a counter addresses a ROM where appropriate step data is stored. Step and Direction are the input signals which represent clock and up / down of counter. This is the ideal solution for a system where there is no microprocessor or it is heavily loaded with other tasks. With a microprocessor, data is stored in ROM / RAM area or each step is successively calculated. PBM 3960/1 is connected like any peripheral addressable device. All parts of stepping can be tailored for specific damping needs etc.
PBM 3960/1
Time when motor is in a compromise position. Time when micro position is correct. Write signal.
Motor position. Writing to channel 1. Writing to channel 2. Time Ideal data = desired position
Write time = incorrect position Useful time = correct position
Double pulse write signal Actual data = true position Normal resolution
Figure 11. Double pulse programming, in- and output signals.
Time when motor is in an intermediate position. Time when micro position is almost correct. Write signal. Motor position. Note that position is always a compromise. Writing to channel 1. Writing to channel 2. Time Useful time = compromise position with equally spaced angles Useful time = almost correct position Single pulse write signal "Ideal data" = desired position Actual data = true position Note increased resolution
Figure 12. Single pulse programming, in- and output signals.
7
PBM 3960/1
Counter
PROM
D0-D7
PBM 3960/1 PBL 3771/1
A0 WR CE Clock Up/Dn CS A1 Vref
Step Direction
Control Logic
Voltage Reference
Figure 13. Typical blockdiagram of an application without a microprocessor. Available as testboard, TB 307i/2.
V CC (+5 V)
+ 0.1 m F 0.1 m F
V MM
10 m F
5 14 D0 V DD Sign1 CD1 7 To m P 15 16 6 17 22 1 D7 V 3 4 2 7 8 9 Phase 1 CD1 V R1 Phase 2 CD 2 V R2 RC GND 12 +5 V 15 kW
3 300 pF
11
CC
3 V
MM1
20 V
MM2
MA1
4
PBM 3960/1
A0 A1 WR CS RESET V Ref
DA1 Sign2 CD2
MB1
1 19
PBL 3771/1
MA2 MB2 C1 10
1 kW
20 19 21
16 15 14
22
+2.5V
V SS 18
DA2
E1 2
C2 13
1 kW
E2 21
5, 6, 17, 18
STEPPER MOTOR
820 pF 1.0 W RS
820 pF 1.0 W RS
Pin numbers refer to DIL package.
GND (V MM )
GND (V CC )
Figure 14. Typical application in a microprocessor based system.
8
PBM 3960/1
This is the ideal solution for a system where there is an available microprocessor with extra capacity and low cost is more essential than simplicity. See typical application, figure 14. increase on the positive edge of the sinecosine curves. Fast current decay is used at higher speeds to avoid current dragging with lost positions and incorrect step angles as a result. Ramping Every drive system has inertia which must be considered in the drive system. The rotor and load inertia play a big role at higher speeds. Unlike the DC motor, the stepper motor is a synchronous motor and does not change its speed due to load variations. Examining a typical stepper motor's torque-versusspeed curve indicates a sharp torque drop-off for the "start-stop without error" curve. The reason for this is that the torque requirements increase by the cube of the speed change. For good motor performance, controlled acceleration and deceleration should be considered even though microstepping will improve overall performance. Double-pulse Programming The normal way is to send two write pulses to the device, with the correct addressing in between, keeping the delay between the pulses as short as possible. Write signals will look as illustrated in figure12. The advantages are: * low torque ripple * correct step angles between each set of double pulses * short compromise position between the two step pulses * normal microstep resolution Single-pulse Programming A different approach is to send one pulse at a time with an equally-spaced duty cycle. This can easily be accomplished and any two adjacent data will make up a microstep position. Write signals will look as in figure 13. The advantages are: * higher microstep resolution * smoother motion The disadvantages are: * higher torque ripple * compromise positions with almostcorrect step angles
User Hints
Never disconnect ICs or PC Boards when power is supplied. Choose a motor that is rated for the current you need to establish desired torque. A high supply voltage will gain better stepping performance even if the motor is not rated for the VMM voltage, the current regulation in PBL 3771/1 will take care of it. A normal stepper motor might give satisfactory result, but while microstepping, a "microsteppingadapted" motor is recommended. This type of motor has smoother motion due to two major differences, the stator / rotor teeth relationship is non-equal and the static torque is lower. The PBM 3960/1 can handle programs which generate microsteps at a desired resolution as well as quarter stepping, half stepping, full stepping, and wave drive. Fast or Slow Current Decay? There is a difference between static and dynamic operation of which the actual application must decide upon when to use fast or slow current decay. Generally slow decay is used when stepping at slow speeds. This will give the benefits of low current ripple in the drive stage, a precise and high overall average current, and normal current
Programming PBM 3960/1
There are basically two different ways of programming the PBM 3960/1. They are called "single-pulse programming" and "double-pulse programming." Writing to the device can only be accomplished by addressing one register at a time. When taking one step, at least two registers are normally updated. Accordingly there must be a certain time delay between writing to the first and the second register. This programming necessity gives some special stepping advantages.
9
PBM 3960/1
Ordering Information
Package Part No.
DIP Tube PLCC Tube PLCC Tape & Reel
PBM 3960/1NS PBM 3960/1QNS PBM 3960/1QNT
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Components. These products are sold only according to Ericsson Components' general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice. 1522-PBM 3960/1 Uen Rev. B (c) Ericsson Components AB 1999
Ericsson Components AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 10

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